1. Field of the Invention
The present invention relates generally to an integrated circuit architecture an more particularly to vertical transistor memories.
2. Background of the Invention
The continuing trend of size reduction of semiconductor memory components in products such as dynamic random access memory (DRAM) has led to development of vertical trench storage capacitors and more recently, vertical access transistors. Both devices are associated with the basic unit of a DRAM, the memory cell. An example of a DRAM cell based on a vertical access transistor is disclosed in U.S. Pat. No. 5,519,236. Use of a vertical trench capacitor and a vertical access transistor facilitates the fabrication of a semiconductor memory cell where F=70 nm or less, while at the same time making it possible to maintain the performance of the access transistor.
Such an integrated circuit architecture includes a transistor array comprising vertical FET transistors and storage capacitors formed vertically in deep trenches. Since the process for forming such devices is new, it is particularly desirable, during wafer processing and in general, to assess the properties and characteristic values of the selection transistors.